1. Field of the Invention
The present invention relates to a method and a device for electronic circuit design and a computer product that enable to reduce the circuit design time.
2. Description of the Related Art
Recently, due to miniaturization and enhancement of speed in various types of electronic circuits, noise analysis and noise suppression during electronic circuit design are becoming increasingly significant. Thus, electronic circuits are designed such that the noise is within a limiting value.
FIG. 16 is a flowchart of a conventional electronic circuit designing method as disclosed in Japanese Patent Laid-Open Publication No. 2002-259481.
Register Transfer Level (RTL) designing is carried out at step SA1. In the RTL designing, functional operations of a logic circuit are represented by using flow of data signals and control signals, to thereby design logic specifications of the electronic circuit to be designed.
The logic specifications designed at step SA1 are input at step SA2, where technology mapping, an optimization process that uses delay period, area etc. as evaluation functions, and a logic synthesis process for generating a cell (logic circuit) at gate level are executed.
A floor plan process is executed at step SA3 for determining an outline layout of each cell on a semiconductor chip. The floor plan process aims at optimizing the size and the electrical characteristics of the semiconductor chip.
At step SA4, based on the outline layout determined at step SA3, each cell is laid out on the layout surface, and the cells are wired with each other. At step SA5, signals are input into all the laid out cells, and a timing analysis is carried out to determine whether the signals are output at predetermined timing and frequency. Because all the cells are subjected to the timing analysis, several days are needed to complete the timing analysis even if a large-scale computer is used.
Whether there is any error in the timing analysis result is determined at step SA6. If the result of determination at step SA6 is “Yes”, in other words, if there is an error in the timing analysis result, redesigning is carried out at step SA4 to prevent occurrence of errors, and layout and wiring of the cells are modified.
Similarly, a timing analysis after the redesigning is carried out at step SA5. Several days are further needed for the timing analysis even if the large-scale computer is used. Whether there is any error in the timing analysis result is determined at step SA6.
If an error occurs again due to a fault in the redesigning, the layout and the wiring of the cells are modified again. Thus, steps SA4 through SA6 are repeated until the result of determination at step SA6 is “No”.
If there is no error in the timing analysis result and the result of determination at step SA6 is “No”, a static noise check is executed at step SA7 for checking static noise (hereinafter, “noise”) in each cell and the wiring that are subjected to the timing analysis.
In the static noise check, capacitance and resistance are computed according to wiring width, wiring layers and wiring length, and noise is computed based on parameters according to parallel section of the wiring and types of cells (driver, receiver etc.).
Whether the noise is within the limiting value (threshold value) is determined at step SA8. If the result of determination at step SA8 is “No”, in other words, if the noise exceeds the limiting value, a redesigning is carried out at step SA4 such that the noise is within the limiting value and there is no error in the timing analysis result, thereby modifying the layout of the cells and the wiring.
Similarly, a timing analysis after the redesigning is carried out at step SA5. Several days are further needed for the timing analysis even if the large-scale computer is used. Whether there is an error in the timing analysis is determined at step SA6. If the result of determination at step SA6 is “Yes”, further redesigning is carried out at step SA4 and the layout of the cells and the wiring is modified.
If the result of determination at step SA6 is “No”, a static noise check after the redesigning is similarly carried out at step SA7. Whether noise after the redesigning is within the limiting value (threshold value) is determined at step SA8. If the result of determination at step SA8 is “No”, in other words, if the noise exceeds the limiting value, a redesigning is carried out at step SA4 such that the noise is within the limiting value and there is no error in the timing analysis result, thereby modifying the layout of the cells and the wiring.
Steps SA4 through SA8 are repeated until the result of determination at step SA8 is “Yes”. If the result of determination at step SA8 is “Yes”, in other words, if there is no error in the timing analysis result and the noise is within the limiting value, manufacturing data is generated at step SA9 for manufacturing the electronic circuits to be designed, based on the layout of each cell and the wiring.
However, in the conventional electronic circuit designing method, because the redesigning pertaining to the layout of the cells and the wiring at step SA4 is carried out based on the experience and the instinct of a designer, further redesigning is often needed, thereby increasing the designing period. Moreover, in the conventional electronic circuit designing method, a large number of electronic circuits are subjected to the designing process, thereby making it difficult to ensure that noise pertaining to all the electronic circuits is within the limiting value.
As shown in FIG. 16, in the conventional electronic circuit designing method, the static noise check is executed at step SA7 after execution of the timing analysis at step SA5.
As explained above, the timing analysis takes a long time.
Further, in the conventional electronic circuit designing method, redesigning of the layout of the circuits and the wiring is carried out at step SA4 if the static noise check is not satisfactory, even if the timing analysis result is satisfactory. Thus, the time-consuming timing analysis needs to be executed again, thereby further increasing the designing period.